Memory interface design for AVS HD video encoder with Level C plus coding order

In video encoder chip, memory interface design is a must to transfer various data between the encoder pipeline and the off-chip memory. Reducing the required off-chip memory bandwidth and improving the memory access efficiency are the two key targets for optimized memory interface design. To achieve these two targets, three novel technologies are proposed in Level C+ coding order based AVS HD video encoder. Firstly, an improved Level C+ coding order with necessary NOP insertions are proposed to achieve 61% bandwidth reduction and make MB pipeline scheduling regular. Secondly, MB-level synchronous memory interface design is proposed by trading off external bandwidth, MB pipeline structure, and internal buffer size. Finally, address mapping and arbitration are proposed to improve the access efficiency by 12%. The optimized memory interface design is successfully implemented on our 1080P@45fps AVS encoder with Xilinx Virtex-6 FPGA at an operating frequency of 200 MHz.