Efficient field-programmable gate array-based reconfigurable accelerator for deep convolution neural network

被引:3
|
作者
Hu, Xianghong [1 ,2 ]
Chen, Taosheng [1 ]
Huang, Hongmin [1 ]
Liu, Zihao [1 ]
Li, Xueming [1 ]
Xiong, Xiaoming [1 ,2 ]
机构
[1] Guangdong Univ Technol, Sch Automat, Guangzhou 510006, Peoples R China
[2] Co Chipeye Microelect Foshan Ltd, Foshan 528225, Peoples R China
关键词
Internet software; Neural nets;
D O I
10.1049/ell2.12121
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Deep convolutional neural networks (DCNNs) have been widely applied in various modern artificial intelligence (AI) applications. DCNN's inference is a process with high calculation costs, which usually requires billions of multiply-accumulate operations. On mobile platforms such as embedded systems or robotics, an efficient implementation of DCNNs is significant. However, most previous field-programmable gate array-based works on accelerators for DCNNs just support one DCNN or just support convolution layers. In order to address this limitation, this work proposes a reconfigurable accelerator. The accelerator is flexible and can support multiple DCNNs and different layer types, such as convolution, pooling, activation function, and full connection layers. It is equipped with a five-level pipeline convolution engine whose main component is two processing element arrays. Furthermore, a design space exploration method is proposed to make full advantage of the proposed accelerator. This accelerator is implemented with the ZYNQ-7 ZC706 evaluation board and achieves a high performance of 53.29 Giga operations per second (GOPS) on AlexNet and 45.09 GOPS on YOLOv2-tiny at 100 MHz. Further performance of the accelerator is compared with the previous works, and it achieves multiple advantages: High performance, high configurability, and efficient resource utilisation.
引用
收藏
页码:238 / 240
页数:3
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