Run-time Hardware Trojan Detection and Recovery for Third-Party IPs in SoC FPGAs

Emerging threats of untrustworthy third-party Intellectual Property (IP) cores (3PIPs) are increasingly raising crucial security concerns about field-programmable gate arrays (FPGAs), especially those used in military, medical, financial, and other critical systems. Detecting Trojans in blackbox 3PIPs is extremely challenging, especially for FPGAs due to their memory nature and dynamic partial or full reconfigurability. This paper presents a novel run-time methodology to prevent, detect, and manage the activation of hardware Trojans inside 3PIPs in FPGAs. Taking advantage of the native parallelism of FPGA designs, an isolated redundancy scheme is proposed to detect and protect a circuit from a Trojan payload. 3PIPs are placed in isolated regions in FPGAs and are controlled by an on-chip ARM processor system. The processor performs partial reconfiguration (PR) to temporarily remove an offending IP for a random amount of time that increases exponentially between each detection, or permanently if the IP has been positively detected as infected. Additionally, security policies are enacted by implementing reference monitors that control the communication between the IPs and various resources inside the FPGA. The design was implemented and verified on a Xilinx SoC FPGA development board using the Trust Hub benchmarks.