Performance constrained multi-application network on chip core mapping

被引：10
|
作者：
Reddy, B. Naresh Kumar [1 ]
Kishan, Dharavath [1 ]
Vani, B. Veena [2 ]
机构：
[1] ICFAI Fdn Higher Educ, Fac Sci & Technol, Hyderabad, Telangana, India
[2] AITS, Tirupati, India
来源：
INTERNATIONAL JOURNAL OF SPEECH TECHNOLOGY | 2019年 / 22卷 / 04期
关键词：
System on chip (SoC); Network on chip (NoC); Core; Spare core placement; DESIGN; AWARE; SOC;
D O I：
10.1007/s10772-019-09636-3
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper proposes the Bat mapping algorithm for efficient application mapping on NoC platform. This approach was assessed by applying it to various benchmark applications. Experimental results revealed that the Bat mapping algorithm has two major contributions compared with existing algorithms: (1) It enables dynamic mapping and efficiently identifies the most favorable mapping system. (2) The simulation tests indicated that the Bat algorithm exhibits higher performance.
引用
收藏
页码：927 / 936
页数：10
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