High-throughput low-cost VLSI architecture for AVC/H.264 CAVLC decoding

被引：8
|
作者：
Lee, G. G. [1 ]
Lo, C. -C. [1 ]
Chen, Y. -C. [1 ]
Lin, H. -Y. [1 ]
Wang, M. -J. [1 ]
机构：
[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 70101, Taiwan
来源：
IET IMAGE PROCESSING | 2010年 / 4卷 / 02期
关键词：
VLC DECODER; EFFICIENT; DESIGN;
D O I：
10.1049/iet-ipr.2008.0064
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This study develops a low-cost very-large-scale-integration (VLSI) hardware architecture for entropy coding with increased throughput using the statistical properties of context-based adaptive variable-length coding (CAVLC) in AVC/H.264. Statistical analyses show that better symbol length prediction was achieved by breaking the recursive dependency among codewords for the multi-symbol decoder implementation. The proposed CAVLC decoder easily meets the real-time requirements for high definition (HD) (1920 x 1088) applications. The clock speed is only 13 MHz under the best case scenario.
引用
收藏
页码：81 / 91
页数：11
相关论文
共 50 条
  • [1] Low Complexity and High Throughput VLSI Architecture for AVC/H.264 CAVLC Decoding
    Lee, Gwo Giun
    Lo, Chia-Cheng
    Chen, Yuan-Ching
    Lei, Sheau-Fang
    Lin, He-Yuan
    Wang, Ming-Jiun
    [J]. ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 1229 - 1232
  • [2] A Novel Low-Cost High-Throughput CAVLC Decoder for H.264/AVC
    Wang, Kyu-Yeul
    Kim, Byung-Soo
    Lee, Sang-Seol
    Kim, Dong-Sun
    Chung, Duck-Jin
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2011, E94D (04): : 895 - 904
  • [3] A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding
    Chang, HC
    Lin, CC
    Guo, JI
    [J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 6110 - 6113
  • [4] A High-Throughput Parallel Hardware Architecture for H.264/AVC CAVLC Encoding
    Shafique, Muhammad
    Tuefek, Adnan Orcun
    Henkel, Joerg
    [J]. 2011 18TH IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING (ICIP), 2011, : 393 - 396
  • [5] High Throughput Parallel Decoding Method for H.264/AVC CAVLC
    Yeo, Donghoon
    Shin, Hyunchul
    [J]. ETRI JOURNAL, 2009, 31 (05) : 510 - 517
  • [6] Architecture Design of Low-power and Low-cost CAVLC Decoder for H.264/AVC
    Huang, Han-Jung
    Fan, Chih-Peng
    [J]. 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, : 1336 - +
  • [7] VLSI implementation of CAVLC decoder for H.264/AVC video decoding
    Chen, Guanghua
    Wan, Fenfang
    Ma, Shiwei
    [J]. HDP'07: PROCEEDINGS OF THE 2007 INTERNATIONAL SYMPOSIUM ON HIGH DENSITY PACKAGING AND MICROSYSTEM INTEGRATION, 2007, : 352 - +
  • [8] High-Throughput Architecture for H.264/AVC CABAC Encoding and Decoding System
    Chang, Yuan-Teng
    [J]. APPLICATIONS OF DIGITAL IMAGE PROCESSING XXXI, 2008, 7073
  • [9] Low-cost VLSI architecture design for forward quantization of H.264/AVC
    Ruiz, G. A.
    Michell, J. A.
    [J]. VLSI CIRCUITS AND SYSTEMS III, 2007, 6590
  • [10] A highly efficient VLSI architecture for H.264/AVC CAVLC decoder
    Lin, Heng-Yao
    Lu, Ying-Hong
    Liu, Bin-Da
    Yang, Jar-Ferr
    [J]. IEEE TRANSACTIONS ON MULTIMEDIA, 2008, 10 (01) : 31 - 42
12345