Fabrication and analysis of CMOS fully-compatible high conductance impact-ionization MOS (I-MOS) transistors

This paper reports on a new process to realize Impact-Ionization MOSFETs (I-MOS) with gate length down to 50nm. This process is an adaptation of a standard 90nm flow, which assures a perfect compatibility with conventional CMOS. The definition of the n(+) and p(+) regions of the I-MOS is based on two shifted lithography steps using the standard source/drain mask. An analytical model for the breakdown voltage of a ID p-i-n diode has also been developed to express the breakdown voltage of I-MOS devices as a function of the gate and intrinsic lengths, and the doping level. This model has been validated by the experimental results. An extremely low experimental device resistance (270 Omega mu m) is reported at a gate length of 55 nm, placing the IMOS architecture favorably with respect to ITRS requirements. This performance is explained by the much higher carrier concentration generated by impact ionization when compared to the conventional MOS. Channel resistance is found negligible and current only limited by the source/drain (S/D) resistance.