High-speed GDDRIII system implementation by channel signal and power integrity factorial design

Implementing single-ended Graphic Double Data Rate III (GDDRIII) interface at 1.6Gbps in production is challenging in the current graphic memory environment. This paper proposes a system design method in the signal and power integrity perspective which could perform the channel factorial electrical analyses to figure out the parameter influence. This methodology could be usefully applied in the budget control and the electrical physical constraint setup on the design phase, and critical parameters could be list down and optimized in the pre-design analysis. We can make a proper compromise among the different design electrical parameters with the corresponding penalties to robustly function up to 1.6Gbps in the graphic controller data transfer.