Efficient structure for FPGA implementation of a configurable multipath fading channel emulator

This paper presents highly efficient hardware structure for FPGA implementation of a configurable multipath fading channel emulator. The design and merits of its three major blocks are also examined in detail, including fading generator with high performance white Gaussian noise (WGN) source, flexible multi-stage interpolator for variable fading rate, and Farrow-based arbitrary multipath delay generator. Using the top-down design flow based on Matlab/Simulink and,System Generator, the whole structure is implemented on a Xilinx XtremeDSP Vertex-4 board. Co-simulation results is also included to demonstrate the functionality and performance of the proposed emulator.