Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template

Resilient circuits are becoming a popular alternative to cope with process, voltage, and temperature variability under ultra-deep-submicron technology. Timing resilient architectures rely on error detection logic (EDL) to detect and recover from timing violations. Different EDLs have been proposed to either reduce the area overheads associated with the additional circuitry or to reduce recovery time, but most of them do not account for testability. This paper proposes a testable EDL (TEDL) architecture for manufacturing and field testing. Fault coverage and area overhead are illustrated on a resilient implementation of Plasma, a 3-stage OpenCore MIPS CPU, which contains the proposed testable EDL circuitry. The results show that 100% of the stuck-at faults of the TEDL are detectable with 4.61% area overhead when compared to the Plasma with the original EDL design.