A 6-bit 2.704Gsps DAC for DS-CDMA UWB

被引：0

作者：

Jung, Jae-Jin ^{[1
]}

Park, Bong-hyuck ^{[2
]}

Choi, Sang-Seong ^{[2
]}

Lim, Shin-Il ^{[3
]}

Kim, Suki ^{[1
]}

机构：

[1] Korea Univ, Seoul, South Korea

[2] Elect & Telecommun Res Inst, Taejon, South Korea

[3] Seokyeong Univ, Seoul, South Korea

来源：

2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS | 2006年

关键词：

CMOS; DAC; UWB; deglitch;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a design of a 6-bit 2.704Gsamples/s D/A converter (DAC) for DS-CDMA UVVB transceivers. The proposed DAC was designed with a current steering segmented 4+2 architecture for high frequency sampling rate. For low glitches, optimized degfitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is -0.081 LSB and the measured differential nonlinearity (DNL) is -0.065 LSB. The DAC implemented in a 0.13um CMOS technology shows s spurious free dynamic range (SFDR) of 41dB at F-signal 300Mhz. The prototype DAC consumes 28mW for a Nyquist sinusoidal output signal at a 2.704Gsamples/s. The chip has an active area of 0.76mm(2).

引用

页码：347 / +

页数：2

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