Satisfiability Modulo Bounded Checking

被引:3
|
作者
Cruanes, Simon [1 ]
机构
[1] Univ Lorraine, CNRS, INRIA, LORIA, F-54000 Nancy, France
来源
AUTOMATED DEDUCTION - CADE 26 | 2017年 / 10395卷
关键词
D O I
10.1007/978-3-319-63046-5_8
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
We describe a new approach to find models for a computational higher-order logic with datatypes. The goal is to find counter-examples for conjectures stated in proof assistants. The technique builds on narrowing [14] but relies on a tight integration with a SAT solver to analyze conflicts precisely, eliminate sets of choices that lead to failures, and sometimes prove unsatisfiability. The architecture is reminiscent of that of an SMT solver. We present the rules of the calculus, an implementation, and some promising experimental results.
引用
收藏
页码:114 / 129
页数:16
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