Gate-bias dependence of low-frequency noise in poly-Si thin-film transistors

In this report, existing models for low-frequency excess electrical noise in poly-Si thin-film transistors are scrutinized and a new model is proposed, in particular, for larg-grain poly-crystalline thin-film transistors. Major noise sources are considered to be located in the grain boundary region, and the grain boundary is modeled as two independent Schottky diodes connected face-to-face. As the gate bias increases, the grain boundary barrier height decreases and the conduction and therefore the noise generation in the grain bulk region become important. Therefore, at low gate bias, grain boundary plays an important role in conduction and noise generation, and at high bias, the number fluctuation involving the oxide traps leading to flat band fluctuation ('unified model' for crystalline-Si MOSFETs) will dominate the noise generation. We calculated the critical gate bias (or barrier height) that severs these two different noise generation regimes. Recently reported experimental results are explained by using this model.