Processor-based Symmetric Transparent BIST

Symmetric Transparent BIST schemes for RAM modnles assure the preservation of the memory contents during periodic testing while at the same time skipping the signature prediction phase required in transparent BIST schemes, achieving considerable reduction in test time. In this work a processor based transparent approach for testing memories is presented. The proposed scheme uses the CPU to perform infield testing. Case study using the MIPS instruction set architecture is provided to demonstrate the applicability of the solution. In order to increase the effectiveness of the solution, a minor hardware modification is proposed that, without imposing any impact on the timing characteristics of the processor significantly decreases the testing time.