Novel process techniques to reduce voids in solder thermal interface materials used for flip-chip package applications

In the present study, the thermal performance of flip chip electronics packages was evaluated by characterizing the amount of voiding present in the Solder Thermal Interface Material (STIM) which is placed between the die and Integrated Heat Spreader (IHS). The study found that the thermal resistance, R-jc (resistance between the Si die and IHS), is dependent upon the amount of voiding present as well as the location of the voiding in the STIM. The study also described the techniques to reduce the STIM voids in flip chip packages and identified the key process parameters to improve the thermal performance. The process parameters varied in this study consisted of STIM thickness, dwell time and temperature, flux weight, and many others, A detailed DOE and statistical analysis were carried out to determine the impact of the parameters mentioned above toward reducing the quantity of voids in the STIM. The analysis showed that for the packages under consideration, the primary process parameters that affect the STIM voiding are cure time, flux weight and TIM thickness.