High Performance Error Tolerant Adders for Image Processing Applications

In this paper, we proposed High Performance Error Tolerant Adders (HPETA) which have an efficient design and quality metrics for inexact computing applications. To achieve high performance, Multiplexer Based Approximate Full Adders (MBAFA) are proposed in the inaccurate part of the HPETA design. High speed, energy and area efficiency have been achieved by the critical path delay reduction and the number of gate-level logic reduction. The performances of the proposed MBAFA and HPETA are investigated by comparing its speed, area, power and accuracy parameters with those of other existing error tolerant adder structures. The investigation of these designs is performed in the Cadence Encounter software using the Application Specific Integration Circuits (ASIC) TSMC 90-nm technology library. From the Simulation results, the proposed MBAFA-I based HPETA-I adder exhibits high speed, area efficiency, low power consumption, less Area-Delay Product (ADP) and 56.25%, 47.98%, 37.58%, 34.03%, 39.32% lesser Power-Delay Product (PDP) than the existing conventional CSLA, SAET-CSLA, ETCSLA, HSETA, HSSSA, respectively.