Built-in self-test with an alternating output

被引:4
|
作者
Bogue, T [1 ]
Gossel, M [1 ]
Jurgensen, H [1 ]
Zorian, Y [1 ]
机构
[1] Univ Waterloo, Dept Comp Sci, Waterloo, ON N2L 3G1, Canada
关键词
D O I
10.1109/DATE.1998.655854
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, a new compaction technique based on signature analysis is presented. Rather than comparing the final signature with the expected one after the test is completed, the binary output of the MISA is converted into an alternating binary signal by two simple cover circuits. An error is indicated whenever the alternation of the output signal is disturbed. This technique results in a higher fault coverage, improved fault diagnosis capability, a greater test autonomy in core-based designs, and early fault notification.
引用
收藏
页码:180 / 184
页数:5
相关论文
共 50 条
  • [1] Built-in self-test
    Zorian, Y
    [J]. MICROELECTRONIC ENGINEERING, 1999, 49 (1-2) : 135 - 138
  • [2] On Built-In Self-Test for Adders
    Pulukuri, Mary D.
    Stroud, Charles E.
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2009, 25 (06): : 343 - 346
  • [3] On Built-In Self-Test for Multipliers
    Pulukuri, Mary D.
    Starr, George J.
    Stroud, Charles E.
    [J]. IEEE SOUTHEASTCON 2010: ENERGIZING OUR FUTURE, 2010, : 25 - 28
  • [4] BUILT-IN SELF-TEST STRUCTURES
    MCCLUSKEY, EJ
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (02): : 29 - 36
  • [5] Economics of built-in self-test
    Ungar, LY
    Ambler, T
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 2001, 18 (05): : 70 - 79
  • [6] On Built-In Self-Test for Adders
    Mary D. Pulukuri
    Charles E. Stroud
    [J]. Journal of Electronic Testing, 2009, 25 : 343 - 346
  • [7] BUILT-IN SELF-TEST TECHNIQUES
    MCCLUSKEY, EJ
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (02): : 21 - 28
  • [8] An Output Response Analyzer Circuit for ADC Built-in Self-Test
    Hsin-Wen Ting
    [J]. Journal of Electronic Testing, 2011, 27 : 455 - 464
  • [9] An Output Response Analyzer Circuit for ADC Built-in Self-Test
    Ting, Hsin-Wen
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2011, 27 (04): : 455 - 464
  • [10] Syndrome signature in output compaction for VLSI built-in self-test
    Das, SR
    Goel, N
    Jone, WB
    Nayak, AR
    [J]. VLSI DESIGN, 1998, 7 (02) : 191 - 201