PISA: Power-robust Multiprocessor Design for Space Applications

Recently the conservative space industry driven by the requirements of novel applications decided to introduce multiprocessor systems. Following the same line of motivation we introduce the PISA multiprocessor chip with improved power robustness for space applications which is successfully produced and tested in IHP 130 nm technology. The paper brings several novelties in respect to the current state-of-the-art. The chip uses the Waterbear framework in which the multiprocessor cores can be dynamically put in one of three different operating modes according to the current application requirements regarding performance, power consumption and fault tolerance. The chip has special power supply architecture with 13 power domains and Adaptive Voltage Scaling (AVS) mechanism based on voltage regulators which imposes a non-standard IC design flow. The measurement results showed that the power supply of the multiprocessor cores can be reduced from the nominal 1,2 V downto 0,82V without compromising power integrity.