A Low-Power Biasing Scheme for the Rail-to-Rail Buffer/Amplifier Applications

In this work, a biasing scheme for economizing the quiescent current of a rail-to-rail buffer/amplifier stages is proposed. In conventional rail-to-rail input amplifiers, both PMOS and NMOS input stages are active and both draw current to make the input stage operational for the full supply range. In this work, in mid-supply conditions, only NMOS input stage is active and the cut-off condition for the NMOS differential input stage is detected via a sense circuit. Whenever the NMOS stage approaches cut-off, the sense path detects the condition and provides current bias for the auxiliary PMOS path. Since only single differential input stage is activated, it saves 35% current for the biasing transistors, which is an important saving if low power is the target of the design. The circuit is designed in Austriamicrosystems (AMS) 0.35 mu m technology and simulated using HSPICE. The proposed design may be suitable for many of the rail-to-rail input stages for the amplifier/buffer or OTA circuits.