A DC-DC Converter with Adaptive Clock Control

被引：0
|
作者：
Kim, Subin [1 ]
Jang, Kichang [1 ]
Park, Chulkyu [1 ]
Choi, Joongho [1 ]
机构：
[1] Univ Seoul, Dept Elect & Comp Engn, Seoul, South Korea
来源：
2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2015年
关键词：
leading edge blanking; PWM; DC-DC converter; current sensing;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, the DC-DC converter for adaptive clock control is presented. The proposed adaptive clock control scheme generates a leading edge blanking (LEB) time which is controlled by load current. The DC-DC converter achieves a high efficiency of more than 90% using supply voltages of 1.8 similar to 3.6V and load currents of 5 similar to 35mA.
引用
收藏
页码：319 / 320
页数：2
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