共 50 条
- [21] Methodology and design challenges for low power implementation at sub 90nm [J]. PROCEEDINGS IEEE SOUTHEASTCON 2007, VOLS 1 AND 2, 2007, : 787 - 794
- [23] Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices [J]. ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 2006, : 110 - +
- [24] Cosmic-ray immune latch circuit for 90nm technology and beyond [J]. 2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 : 492 - 493
- [25] Application of 3D scatterometry to contacts and vias at 90nm and beyond [J]. Metrology, Inspection, and Process Control for Microlithography XIX, Pts 1-3, 2005, 5752 : 1266 - 1270
- [26] Experimental Study and Analysis of Soft Errors in 90nm Xilinx FPGA and Beyond [J]. RADECS 2007: PROCEEDINGS OF THE 9TH EUROPEAN CONFERENCE ON RADIATION AND ITS EFFECTS ON COMPONENTS AND SYSTEMS, 2007, : 641 - +
- [27] Design and Challenges of Passive UHF RFID Tag in 90nm CMOS Technology [J]. EDSSC: 2008 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, 2008, : 69 - 72
- [29] Integration solutions for 90nm BEOL [J]. ADVANCED METALLIZATION CONFERENCE 2004 (AMC 2004), 2004, : 89 - 95
- [30] Meeting manufacturing metrology challenges at 90 nm and beyond [J]. MICRO, 2005, 23 (07): : 31 - 41