LSB page refresh based retention error recovery scheme for MLC NAND Flash

被引：1
|
作者：
Ma, Haozhi [1 ]
Liu, Lifang [1 ]
Pan, Liyang [1 ,2 ]
Xu, Jun [1 ,2 ]
机构：
[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
[2] Tsinghua Natl Lab Informat Sci & Technol, Beijing 100084, Peoples R China
来源：
SCIENCE CHINA-INFORMATION SCIENCES | 2016年 / 59卷 / 04期
基金：
中国国家自然科学基金;
关键词：
NAND flash; reliability; retention; refresh; data error recovery;
D O I：
10.1007/s11432-015-5440-5
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
NAND Flash memories present inevitable decline in reliability due to scaling down and multi-level cell (MLC) technology. High retention error rate in highly program/erase (P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit (LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Compared with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.
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收藏
页数：11
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