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- [1] Gate oxide damage and charging characterization in 0.13μm, triple oxide (1.7/2.2/5.2nm) bulk technology 2002 7TH INTERNATIONAL SYMPOSIUM ON PLASMA- AND PROCESS-INDUCED DAMAGE, 2002, : 10 - 13
- [2] Characterization of plasma damage in plasma nitrided gate dielectrics for advanced CMOS dual gate oxide process 2002 7TH INTERNATIONAL SYMPOSIUM ON PLASMA- AND PROCESS-INDUCED DAMAGE, 2002, : 41 - 44
- [3] A triple gate oxide CMOS technology using fluorine implant for system-on-a-chip 2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, : 148 - 149
- [4] PMOS NBTI analysis of a 45nm CMOS-SOI Process with Nitrided Gate Dielectric 2012 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP FINAL REPORT, 2012, : 199 - 202
- [5] A triple gate oxide logic process for 90nm manufacturing technology 2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 719 - 722
- [7] 45-nm node NiSiFUSI on nitrided oxide bulk CMOS fabricated by a novel integration process IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 231 - 234
- [8] EXPLORING THE EFFECT OF GATE OXIDE PROCESS ON ELECTRICAL PERFORMANCE OF CMOS DEVICE CONFERENCE OF SCIENCE & TECHNOLOGY FOR INTEGRATED CIRCUITS, 2024 CSTIC, 2024,