Duty cycle aware application design using FPGAs

被引：1
|
作者：
Mohanty, S [1 ]
Prasanna, VK [1 ]
机构：
[1] Univ So Calif, Los Angeles, CA 90089 USA
来源：
12TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS | 2004年
关键词：
D O I：
10.1109/FCCM.2004.30
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Duty cycle is the proportion of time a device is active. Therefore, based on the duty cycle specification, application (implemented using the device) execution can be modeled as alternate active and inactive phases. For FPGAs, during inactive phases, energy is dissipated due to leakage current and clock signal distribution. If the duration of the inactive phases is significantly larger than that of the active phases, optimizing energy dissipation during inactive phases contributes significantly towards the overall energy efficiency. We present a design tool for the evaluation of various optimization techniques such as shutting down FPGAs, transitioning to a low power state, or leaving as it is to minimize overall energy dissipation. We illustrate the tool through energy efficient design of a target tracking application using FPGAs.
引用
收藏
页码：338 / 339
页数：2
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