FPGA-based high area efficient time-to-digital IP design

被引：0

作者：

Lin, Min-Chuan ^{[1
]}

Tsai, Guo-Ruey ^{[1
]}

Liu, Chun-Yi ^{[1
]}

Chu, Shi-Shien ^{[1
]}

机构：

[1] Kun Shan Univ, Dept Elect Engn, Tainan, Taiwan

来源：

TENCON 2006 - 2006 IEEE REGION 10 CONFERENCE, VOLS 1-4 | 2006年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper proposes a novel design for a highly area efficient FPGA-based TDC (Time to Digital Converter) IP (Intelligent Property) with resolution less than 30ps. To avoid the unpredictable internal place and route (P&R) delay, a modified ring oscillator is presented By integrating the gates delay and P&R delay, a design by combining Schematic and VHDL codes, can generate a predictable and stable TDC module built in a Xilinx FPGA.

引用

页码：1075 / +

页数：2

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