FPGA Implementation of Model Predictive Direct Current Control

An FPGA implementation of Model Predictive Direct Current Control (MPDCC) is reported in this paper. A central scheduler enumerates switching sequences and assigns these to several explorer units, which predict the system response and compute their associated cost. The proposed FPGA design is scalable, modular and requires little hardware resources. A fivelevel active neutral point clamped inverter with a medium-voltage induction machine is considered. The MPDCC scheme controls the machine's stator currents, the neutral point potential and the inverter's phase capacitor voltages at a low switching frequency.