Performance Analysis Of Efficient Carry Select Adder

被引：0

作者：

Sangeetha, M. ^{[1
]}

Balaji, S. ^{[1
]}

Praveen, John Paul A. ^{[1
]}

Mohanraj, R. ^{[1
]}

机构：

[1] BIHER, Dept Elect & Commun Engn, Chennai, Tamil Nadu, India

来源：

JOURNAL OF MECHANICS OF CONTINUA AND MATHEMATICAL SCIENCES | 2019年

关键词：

CSLA; Area; delay performance; low power design and arithmetic unit;

D O I：

10.26782/jmcms.spl.2019.08.00046

中图分类号：

O3 [力学];

学科分类号：

08 ; 0801 ;

摘要：

Carry Select Adder (CSA) has multiplexer and also Ripple Carry Adder (RCA). Logical operation in traditional CSLA and BEC depends on CSLA is used to analyze the dependence in data and logic operations which is redundant is identified. Operation speed is an constraint which is obtained when multipliers are designed. Electronic components require more battery backup. A proposed adder speeds 40% to 90%. The reported work decreases the area and delay by the use of 2:1 mux. And implement the result by using FPGA.

引用

页码：380 / 386

页数：7

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