Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic

被引：6

作者：

Osorio, MCB ^{[1
]}

Sampaio, CA ^{[1
]}

Reis, AI ^{[1
]}

Ribas, RP ^{[1
]}

机构：

[1] UFRGS, Inst Informat, BR-91501970 Porto Alegre, RS, Brazil

来源：

SBCCI2004:17TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS | 2004年

关键词：

digital circuits; adder; ECDL; CMOS;

D O I：

10.1145/1016568.1016619

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents an enhanced 32-bit carry look-ahead (CLA) adder implemented using the multi-output enable/disable CMOS differential logic (MOECDL) style. The MOECDL structure proposed represents a promising technique for iterative networks and self-timed circuits. The recursive property of CLA algorithm has been efficiently exploited to demonstrate the advantages of multiple-output structures. The 32-bit MOECDL CLA circuit has been designed into a standard 0.5 mum CMOS technology. Comparison to the known DCVS style is presented through electrical simulation.

引用

页码：181 / 185

页数：5

共 24 条

[21] Comparative Analysis of 8 Bit Carry Skip Adder using CMOS and PTL Techniques with Conventional MOSFET at 32 Nanometer Regime
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[24] Preventing Differential Cryptanalysis Attacks Using a KDM Function and the 32-Bit Output S-Boxes on AES Algorithm Found on the Internet of Things Devices
Muthavhine, Khumbelo Difference
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[J]. CRYPTOGRAPHY, 2022, 6 (01)

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