Modified Scan Flip-Flop for Low Power Testing

被引：16

作者：

Mishra, Amit ^{[1
]}

Sinha, Nidhi ^{[1
]}

Satdev ^{[1
]}

Singh, Virendra ^{[1
]}

Chakravarty, Sreejit ^{[2
]}

Singh, Adit D. ^{[3
]}

机构：

[1] Indian Inst Sci, Bangalore 560012, Karnataka, India

[2] LSI Corp, Milpitas, CA USA

[3] Auburn Univ, Auburn, AL 36849 USA

来源：

2010 19TH IEEE ASIAN TEST SYMPOSIUM (ATS 2010) | 2010年

关键词：

Low power testing; Launch on capture; Launch on shift; Stuck-at faults; Scan flip-flop;

D O I：

10.1109/ATS.2010.69

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Scanning of test vectors during testing causes unnecessary and excessive switching in the combinational circuit compared to that in the normal operation. In this paper, we propose a modified design of a scan flip-flop which eliminates the power consumed due to unnecessary switching in the combinational circuit during scan shift, with a little impact on performance. The new scan flip-flop disables the slave latch during scan, and uses an alternate low cost dynamic latch in the scan path instead. Methods for generating slave latch disable control signal are also presented.

引用

页码：367 / 370

页数：4

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