Standard-cell design architecture options below 5nm node: the ultimate scaling of FinFET and Nanosheet

被引：20

作者：

Sherazi, S. M. Yasser ^{[1
]}

Cupak, Miroslav ^{[1
]}

Weckx, P. ^{[1
]}

Zografos, O. ^{[1
]}

Jang, D. ^{[1
]}

Debacker, P. ^{[1
]}

Verkest, D. ^{[1
]}

Mocuta, A. ^{[1
]}

Kim, R. H. ^{[1
]}

Spessot, A. ^{[1
]}

Ryckaert, J. ^{[1
]}

机构：

[1] IMEC, Dept Log Technol, Kapeldreef 75, B-3001 Heverlee, Belgium

来源：

DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY XIII | 2019年 / 10962卷

关键词：

Standard Cell Design; Track height reduction; Scaling using DTCO; Advanced technology node; Tight metal pitch; Multi-level middle of line; Scaling boosters; FinFET;

D O I：

10.1117/12.2514569

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

The targeted N3 technology node at IMEC is being redefined with respect to the poly pitch, as compared to the previous node definitions [1,2]. The overall industry trend of poly pitch scaling is slowing down, due to difficulties in keeping pace with device performance and yield issues. However, the metal pitch continues to scale down, which implies that direct pitch scaling will not lead to the most optimum scaling. Therefore, Standard Cell (SDC) track height reduction is a knob that can be used to achieve advances in the scaling of the technology to preserve Moore's law. Here we present some of the options for the standard cell design that can enable an N3 technology node by using Design-Technology co-optimization (DTCO).

引用

页数：15

共 6 条

[1] Track height reduction for standard-cell in below 5nm node: How low can you go?
Sherazi, S. M. Yasser
Chae, Jung Kyu
Debacker, P.
Matti, L.
Raghavan, P.
Gerousis, V.
Verkest, D.
Mocuta, A.
Kim, R. H.
Spessot, A.
Ryckaert, J.
DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY XII, 2018, 10588
[2] CFET Standard-cell design down to 3Track height for node 3nm and below
Sherazi, S. M. Y.
Kyu, J.
Debacker, P.
Matti, L.
Verkest, D.
Mocuta, A.
Kim, R. H.
Spessot, A.
Dounde, A.
Ryckaert, J.
DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY XIII, 2019, 10962
[3] Architectural strategies in standard-cell design for the 7 nm and beyond technology node
Sherazi, Syed Muhammad Yasser
Chava, Bharani
Debacker, Peter
Bardon, Marie Garcia
Schuddinck, Pieter
Firouzi, Farshad
Raghavan, Praveen
Mercha, Abdelkarim
Verkest, Diederik
Ryckaert, Julien
JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, 2016, 15 (01):
[4] Accurate Performance Evaluation for the Horizontal Nanosheet Standard-Cell Design Space Beyond 7nm Technology
Lee, Y. M.
Na, M. H.
Chu, A.
Young, A.
Hook, T.
Liebmann, L.
Nowak, E. J.
Baek, S. H.
Sengupta, R.
Trombley, H.
Miao, X.
2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2017,
[5] 5nm FinFET Standard Cell Library Optimization and Circuit Synthesis in Near- and Super-Threshold Voltage Regimes
Xie, Qing
Lin, Xue
Wang, Yanzhi
Dousti, Mohammad Javad
Shafaei, Alireza
Ghasemi-Gol, Majid
Pedram, Massoud
2014 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2014, : 425 - 430
[6] Design of a high performance CNFET 10T SRAM cell at 5nm technology node
Yang, Zihao
Yin, Minghui
You, Yunxia
Li, Zhiqiang
Liu, Xin
Zhang, Weihua
IEICE ELECTRONICS EXPRESS, 2023, 20 (12):

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