Retiming Arithmetic Datapaths using Timed Taylor Expansion Diagrams

This paper describes an extension to the Taylor Expansion Diagrams (TED), called Timed TEDs, which makes it possible to represent sequential arithmetic datapaths. Timed TEDs enable register and clock period minimization while performing factorizations and common sub expression eliminations in the data flow graph (DFG). Specifically, timed TEDs allow a wider range of retiming options as the computations in the DFG can be modified while performing retiming. In this paper we discuss the formalism of timed TEDs and the restrictions it imposes on the TED variable ordering.