Retiming Arithmetic Datapaths using Timed Taylor Expansion Diagrams

被引：1
|
作者：
Gomez-Prado, Daniel [1 ]
Kim, Dusung [1 ]
Ciesielski, Maciej [1 ]
Boutillon, Emmanuel [2 ]
机构：
[1] Univ Massachusetts Amherst, Amherst, MA 01003 USA
[2] Univ Bretagne Sud, Lab STICC, Lorient, France
来源：
2010 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP (HLDVT) | 2010年
基金：
美国国家科学基金会;
关键词：
D O I：
10.1109/HLDVT.2010.5496664
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes an extension to the Taylor Expansion Diagrams (TED), called Timed TEDs, which makes it possible to represent sequential arithmetic datapaths. Timed TEDs enable register and clock period minimization while performing factorizations and common sub expression eliminations in the data flow graph (DFG). Specifically, timed TEDs allow a wider range of retiming options as the computations in the DFG can be modified while performing retiming. In this paper we discuss the formalism of timed TEDs and the restrictions it imposes on the TED variable ordering.
引用
收藏
页码：33 / 39
页数：7
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