A high-level data path allocation algorithm based on BIST testability metrics

被引：0
|
作者：
Yang, LT [1 ]
Muzio, J [1 ]
机构：
[1] St Francis Xavier Univ, Dept Comp Sci, Antigonish, NS B2G 2W5, Canada
来源：
ICM 2002: 14TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS | 2002年
关键词：
Built-In Self-Test; testability metrics; controllability; observability; module and register allocation;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we describe a BIST testability metric-based high-level data path allocation algorithm to facilitate Built-In Self-Test designs. We will describe register transfer level data path testability metrics to evaluate various BIST configurations and make improvement decision during the data path allocation. With a variety of benchmarks, we demonstrate the advantage of our approach compared with other conventional approaches.
引用
收藏
页码：232 / 236
页数：5
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