Design of less time delay Multiplier using vedic mathematics

被引：0
|
作者：
Dogra, Megha [1 ]
Balamurugan, V [2 ]
机构：
[1] Sathyabama Univ, VLSI Design, Chennai, Tamil Nadu, India
[2] Sathyabama Univ, Fac Elect & Elect, Chennai, Tamil Nadu, India
来源：
PROCEEDINGS OF 2016 ONLINE INTERNATIONAL CONFERENCE ON GREEN ENGINEERING AND TECHNOLOGIES (IC-GET) | 2016年
关键词：
MCLA (modified carry look ahead adder); MPFA(metamorphosis ofpartialfull adder); VEDIC; Multiplier;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In digital circuit multiplier plays an important role. They are useful in many applications like arithmetic and logic unit, MAC(multiplication and accumulator) and DSP(digital signal processing). In this paper a VEDIC multiplier proposed "urdhva tiryagbhyam Multiplication" using MCLA(Modified Carry Look ahead Adder). Speed is one of the parameter of any digital circuit so to improve the speed of the multiplication the above mentioned multiplier is proposed and the results are compared with the existing multiplier. The multiplier using Modified carry look ahead circuit is more efficient and lesser delay compared with existing one.
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页数：3
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