An efficient VLSI architecture for the computation of 1-D Discrete Wavelet Transform

被引：2
|
作者：
Premkumar, AB [1 ]
Madhukumar, AS [1 ]
机构：
[1] Nanyang Technol Univ, Sch Appl Sci, Singapore 639798, Singapore
来源：
ICICS - PROCEEDINGS OF 1997 INTERNATIONAL CONFERENCE ON INFORMATION, COMMUNICATIONS AND SIGNAL PROCESSING, VOLS 1-3: THEME: TRENDS IN INFORMATION SYSTEMS ENGINEERING AND WIRELESS MULTIMEDIA COMMUNICATIONS | 1997年
关键词：
D O I：
10.1109/ICICS.1997.652169
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a new architecture for VLSI implementation of one dimensional Discrete Wavelet Trans-form (DWT). The architecture uses single filter for the generation of both DWT coefficients and scaling: function for orthogonal wavelets as opposed to the conventional two filter approach. For subsequent levels, we rely on the fold back architecture principles which interleave the decimated scaling functions back into the filters for the subsequent DWT coefficients. Limited use of memory in the design enables efficient implementation of the DWT computation in VLSI.
引用
收藏
页码：1180 / 1184
页数：3
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