Improved Delay-Based Phase-Locked. Loop for Grid- Tied Inverter to Improve the Performance under Weak Grid

In recent years, the grid-connected inverter and its control in the weak grid case have drawn wide attentions. For the grid synchronization, a phase-locked loop (PLL) is usually needed. Typically, the delay-based I'LL is widely used in the single-phase application. However, when a large grid impedance exists at the point of common coupling (PCC) in the weak grid case, the inverter with the delay-based PLL cannot work well or even be unstable. Hence, this paper aims at proposing a robust method to improve the delay-based P1.1, performance with the large grid impedance. First, the system modelling is established. Then, an additional grid current feedforward is proposed to add into the delay-based PLL It has been shown that the proposed method equivalently adds an adjustable impedance in series to the original inverter output impedance, and improves the behaviors in weak grid cases. The selection of parameters has been emphasized for maintaining the high robustness. At last, comparative waveforms have verified that the single-phase inverter with the proposed method can perform well even with the large grid impedance.