共 50 条
- [2] A novel PWM scheme to eliminate common-mode voltage in three-level voltage source inverter [J]. PESC 98 RECORD - 29TH ANNUAL IEEE POWER ELECTRONICS SPECIALISTS CONFERENCE, VOLS 1 AND 2, 1998, : 269 - 274
- [3] Common-Mode Voltage Eliminated Three-Level Inverter using a Three-Level Flying-Capacitor Inverter and Cascaded H-Bridge [J]. IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS, DRIVES AND ENERGY SYSTEMS (PEDES 2012), 2012,
- [4] Common-Mode Voltage Reduction with Two-Phase Modulation in Three-Level PWM Inverter [J]. 2013 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE), 2013, : 5349 - 5354
- [5] Common-Mode Voltage Eliminated 2-level PWM Inverter Based on a Cascaded 3-level Inverter [J]. 2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 561 - 566
- [6] Common-mode voltage mitigation of diode clamped three-level inverter [J]. Dianli Zidonghua Shebei/Electric Power Automation Equipment, 2018, 38 (01): : 66 - 73
- [9] Reduction of Common Mode voltage for Three-Level Inverter using Novel switching sequences [J]. 2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 984 - 989