An Efficient Four-State Zero Common-Mode Voltage PWM Scheme With Reduced Current Distortion for a Three-Level Inverter

被引:40
|
作者
Tam-Khanh Tu Nguyen [1 ]
Nho-Van Nguyen [1 ]
机构
[1] Ho Chi Minh City Univ Technol, VNU HCM, Dept Elect Engn, Ho Chi Minh 70000, Vietnam
关键词
Common-mode voltage (CMV); current ripple; harmonic distortion; pulse width modulation (PWM); switching sequences; three-level (3L) neutral-point-clamped (NPC) inverter; CASCADED MULTILEVEL INVERTERS; INDUCTION-MOTOR DRIVES; CURRENT RIPPLE; CLAMPED INVERTER; RMS;
D O I
10.1109/TIE.2017.2733418
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, a new carrier-based pulse width modulation (PWM) strategy providing common-mode voltage (CMV) elimination and reduced current ripple in a three-level neutral-point-clamped inverter is introduced. The employed switching sequences are made up of the three zero CMV (ZCMV) vectors, and one among the three vectors is applied at two ends of a half-carrier cycle. The output current ripple characteristics pertaining to those switching sequences are investigated. In a carrier cycle, the root-mean-square current ripple minimization is analyzed and an optimal sequence is derived accordingly. The presented PWM scheme results in a considerably reduced current harmonic distortion in a wide modulation region as compared to the two existing ZCMV schemes on the same average switching frequency. Also, an implementation of sawtooth-carrier-based PWM patterns is proposed for further improvement of the harmonic performance. The algorithm requires small computational burden and is straightforward for an online implementation. Simulation and experimental results are both provided to validate the good performance of the proposed PWM method.
引用
收藏
页码:1021 / 1030
页数:10
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