A high-speed, current-steering digital-to-analog converter in 0.6-um CMOS

A 10-bit, current-steering, high-speed CMOS D/A is presented using a delay technique to increase the speed of converter. Simulation results show that the spurious-free-dynamic-range (SFDR) is better than 62dB for sampling frequency up to 400M Sample/s and signals from do to Nyquist. Monte-Carlo simulations show that differential non-linearity (DNL) and integral non-linearity (INL) are better than 0.03 least significant bit (LSB) and 0.24 LSB, respectively. The estimated INL-yield is 99.7% and the design is based on it. The converter dissipates less than 250mW from a 3V power supply when operating at 400MHz. The circuit has been designed in a standard 0.6mum-CMOS process. The results have been checked with all process corners from -40degreesC to 85degreesC and power supply from 2.7V to 3.3V.