Using domain partitioning in wrapper design for IP cores under power constraints

被引：2

作者：

Yu, Thomas Edison ^{[1
]}

Yoneda, Tomokazu ^{[1
]}

Zhao, Danella ^{[2
]}

Fujiwara, Hideo ^{[1
]}

机构：

[1] Nara Inst Sci & Technol, Grad Sch Informat Sci, Kansai Sci City 6300192, Japan

[2] Univ Louisiana Lafayette, Ctr Adv Comp Studies, Lafayette, LA 70504 USA

来源：

25TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2007年

基金：

日本学术振兴会;

关键词：

multi-clock domain; wrapper design; SoC; embedded core test; test scheduling;

D O I：

10.1109/VTS.2007.86

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a novel design method for power-aware test wrappers targeting embedded cores with multiple clock domains. We show that effective partitioning of clock domains combined with handwidth conversion and gated-clocks would yield shorter test times due to greater flexibility when determining optimal test schedules especially under tight power constraints.

引用

页码：369 / +

页数：3

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