A low thermal budget high performance 0.25-0.18 μm merged logic device and dynamic random access memory application

Merged dynamic random access memory (DRAM) with logic technology has been widely investigated because of to its high on-chip memory bandwidth, low power consumption, customized memory size, and small footprint advantages. A low thermal budget 0.25-0.18 mu m embedded DRAM technology has been developed to merge a high-performance logic device and high-density DRAM on the same chip. In this newly developed technology, shallow trench isolation, a triple well, TiSix polycide, titanium salicide, a self-aligned contact poly-via and a low thermal budget oxide-nitride-oxide (ONO) as well as Ta2O5 capacitor dielectrics used for 1 Gbit DRAM design, are being applied. A 32 Mbit synchronous DRAM macro was designed based on this technology and is proposed offered as a drop-in module for embedded DRAM applications.