A stochastic wire-length distribution for gigascale integration (GSI) - Part II: Applications to clock frequency, power dissipation, and chip size estimation

被引：66

作者：

Davis, JA ^{[1
]}

De, VK ^{[1
]}

Meindl, JD ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Microelect Res Ctr, Atlanta, GA 30332 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1998年 / 45卷 / 03期

关键词：

average wire length; critical path; die area estimation; power dissipation model; Rent's Rule; wire-length distribution;

D O I：

10.1109/16.661220

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Based on Rent's Rule, a well-established empirical relationship, a complete wire-length distribution for on-chip random logic networks is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density and minimum chip size.

引用

页码：590 / 597

页数：8

共 3 条

[1] Stochastic wire-length distribution for gigascale integration (GSI) - Part II: Applications to clock frequency, power dissipation, and chip size estimation
Georgia Inst of Technology, Atlanta, United States
IEEE Trans Electron Devices, 3 (590-597):
[2] A stochastic wire-length distribution for gigascale integration (GSI) - Part I: Derivation and validation
Davis, JA
De, VK
Meindl, JD
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (03) : 580 - 589
[3] A stochastic wire length distribution for gigascale integration (GSI)
Davis, JA
De, VK
Meindl, JD
PROCEEDINGS OF THE IEEE 1997 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1997, : 145 - 150

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