On the automatic generation of test programs for path-delay faults in microprocessor cores

被引：0

作者：

Bernardi, P. ^{[1
]}

Grosso, M. ^{[1
]}

Sanchez, E. ^{[1
]}

Reorda, M. Sonza ^{[1
]}

机构：

[1] Politecn Torino, Dipartimento Automat & Informat, Turin, Italy

来源：

ETS 2007: 12TH IEEE EUROPEAN TEST SYMPOSIUM, PROCEEDINGS | 2007年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Delay testing is mandatory for guaranteeing the correct behavior of today's high-performance microprocessors. Several methodologies have been proposed to tackle this issue resorting to additional hardware or to software self-test techniques. Software techniques are particularly promising as they resort to Assembly programs in normal mode of operation, without requiring circuit modifications; however, the problem of generating effective and efficient test programs for path-delay fault detection is still open. This paper presents an innovative approach for the generation of path-delay self-test programs for microprocessors, based on an evolutionary algorithm and on ad-hoc software simulation/hardware emulation heuristic techniques. Experimental results show how the proposed methodology allows generating suitable test programs in reasonable times.

引用

页码：179 / +

页数：2

共 50 条

[1] A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores
Bernardi, P.
Grosso, M.
Sanchez, E.
Reorda, M. Sonza
[J]. MTV 2008: NINTH INTERNATIONAL WORKSHOP ON MICROPROCESSOR TEST AND VERIFICATION, PROCEEDINGS, 2009, : 103 - 108
[2] Test program synthesis for path delay faults in microprocessor cores
Lai, WC
Krstic, A
Cheng, KT
[J]. INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, : 1080 - 1089
[3] Exploiting MOEA to automatically geneate test programs for path-delay faults in microprocessors
Bernardi, P.
Christou, K.
Grosso, M.
Michael, M. K.
Sanchez, E.
Reorda, M. Sonza
[J]. APPLICATIONS OF EVOLUTIONARY COMPUTING, PROCEEDINGS, 2008, 4974 : 224 - +
[4] Automatic path-delay fault test generation for combined resistive vias, resistive bridges, and capacitive crosstalk delay faults
Chary, S
Bushnell, ML
[J]. 19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2005, : 413 - 418
[5] Test generation for path-delay faults in one-dimensional iterative logic arrays
Abdulrazzaq, NM
Gupta, SK
[J]. INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, : 326 - 335
[6] Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests
Marwan A. Gharaybeh
Michael L. Bushnell
Vishwani D. Agrawal
[J]. Journal of Electronic Testing, 1997, 11 : 55 - 67
[7] Classification and test generation for path-delay faults using single struck-at fault tests
Gharaybeh, MA
Bushnell, ML
Agrawal, VD
[J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1997, 11 (01): : 55 - 67
[8] Classification and test generation for path-delay faults using single struck-at fault tests
Gharaybeh, Marwan A.
Bushnell, Michael L.
Agrawal, Vishwani D.
[J]. Journal of Electronic Testing: Theory and Applications (JETTA), 1997, 11 (01): : 55 - 67
[9] A BIST scheme for the detection of path-delay faults
Mukherjee, N
Chakraborty, TJ
Bhawmik, S
[J]. INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS, 1998, : 422 - 431
[10] An Approach to Automatic Test Generation for Verification of Microprocessor Cores
Gagarina, Larisa G.
Garashchenko, Anton V.
Shiryaev, Alexey P.
Fedorov, Alexey R.
Dorogova, Ekaterina G.
[J]. PROCEEDINGS OF THE 2018 IEEE CONFERENCE OF RUSSIAN YOUNG RESEARCHERS IN ELECTRICAL AND ELECTRONIC ENGINEERING (EICONRUS), 2018, : 1490 - 1491

← 1 2 3 4 5 →