Ultra low power CORDIC processor for wireless communication algorithms

被引：8

作者：

Sarrigeorgidis, K ^{[1
]}

Rabaey, J ^{[1
]}

机构：

[1] Univ Calif Berkeley, EECS Dept, Berkeley, CA 94720 USA

来源：

JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 2004年 / 38卷 / 02期

关键词：

wireless communications; cordic arithmetic; least squares; QR decomposition; redundant arithmetic; low power design;

D O I：

10.1023/B:VLSI.0000040424.11334.34

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

We designed and implemented an ultra low power CORDIC processor which targets the implementation of advanced wireless communications algorithms based on Givens rotations and Householder reflections. We propose a modified CORDIC algorithm and architecture, and we elaborate on the low power architectural and algorithmic techniques for minimizing its power consumption. Our CORDIC implementation consumes, in rotate mode, on average 50 muW @ 10 MHz under 1 V supply voltage in a .25 mum technology.

引用

页码：115 / 130

页数：16

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