Software validation facilities.

This paper is a status report on the development of Software Validation Facilities (SVF) supporting the commonly used microprocessors within the ESA space programmes. The Software Validation Facility is intended to support all phases of the test and verification of on-board software. It is an especially valuable support facility in the absence of the target hardware or when parallel development of target software and hardware takes place. The Software Validation Facility is a software test bench which includes a copy of the target microprocessor and a simulated model of the environment. This architecture is referred to as a hardware-in-the-loop emulation system because it contains a copy of the target processor for which the on-board software was designed. The chosen architecture opens the possibility for test and verification of the on-board software, configured exactly as it will fly when it is integrated onto the spacecraft. This is a powerful test-bench in which full visibility into the on-board software is maintained, while it is executing under its real-life functional and operational constraints. The paper presents the architecture of the Software Validation facility and the family of emulators currently supported. Additionally it describes the available basic tools which support the various steps of on-board software test and validation activities. The paper further describes the on-going and future activities within the support tools and within a library of configurable environment simulation objects.