Quantifying software performance, reliability and security: An architecture-based approach

被引:43
|
作者
Sharma, Vibhu Saujanya [1 ]
Trivedi, Kishor S.
机构
[1] Indian Inst Technol, Dept Comp Sci & Engn, Kanpur 208016, Uttar Pradesh, India
[2] Duke Univ, Dept Elect & Comp Engn, Durham, NC 27708 USA
关键词
software architecture; performance; reliability; security; Markov models;
D O I
10.1016/j.jss.2006.07.021
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
With component-based systems becoming popular and handling diverse and critical applications, the need for their thorough evaluation has become very important. In this paper we propose an architecture-based unified hierarchical model for software performance, reliability, security and cache behavior prediction. We employ discrete time Markov chains (DTMCs) to model software systems and provide expressions for predicting the overall behavior of the system based on its architecture as well as the characteristics of individual components. This approach also facilitates the identification of various bottlenecks. We illustrate its use through some case studies and also provide expressions to perform sensitivity analysis. (c) 2006 Elsevier Inc. All rights reserved.
引用
收藏
页码:493 / 509
页数:17
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