A high performance soft decision viterbi decoder for WLAN and broadband applications

This paper presents a configurable 3-bit soft decision Viterbi decoder implementation that meets the requirements for WLAN and broadband applications. The programmable design supports a constraint length K=7 soft decision Viterbi decoder (SDVD) realization with a code rate (R) of 1/2 and traceback lengths (TBL) of 35 and 50 symbols. To assure a throughput of 155 Mbps, an architecture incorporating 32 Add Compare Select (ACS) units operating in parallel has been selected The design incorporates a built-in self-test for operation at the rated throughput. The VHDL simulation results are verified against a functional model of the Viterbi decoder reflecting the hardware architecture in the Matlab simulation environment. The decoder architecture is defined in VHDL and the circuit is simulated, synthesized, and implemented on a Xilinx XC2VP100-1704ff-5 FPGA device.