共 50 条
- [41] Complexity of Representations of Multiple-Output Boolean Functions in the Reversible Logic Circuits PROCEEDINGS OF THE XIX IEEE INTERNATIONAL CONFERENCE ON SOFT COMPUTING AND MEASUREMENTS (SCM 2016), 2016, : 374 - 376
- [42] Multi-level factorisation technique for pass transistor logic IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1998, 145 (01): : 48 - 54
- [43] Design of submicrometer CMOS differential pass-transistor logic circuits IEEE Journal of Solid-State Circuits, 1991, 26 (09): : 1249 - 1258
- [45] Multi-input variable-threshold circuits for multi-valued logic functions 30TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2000, : 27 - 32
- [46] Generating digital circuits tests using multi-valued logic and inductive statements Engineering Simulation, 1997, 14 (01): : 75 - 82
- [47] Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits 40TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC ISMVL 2010, 2010, : 128 - 133
- [48] Multi-Valued Logic Based on Probability-Generated Aggregators 2014 IEEE 28TH CONVENTION OF ELECTRICAL & ELECTRONICS ENGINEERS IN ISRAEL (IEEEI), 2014,
- [50] Symmetric ternary logic based multi-valued learning network Jisuanji Xuebao/Chinese Journal of Computers, 21 (06): : 553 - 559