CMOS fully integrated reconfigurable power amplifier with efficiency enhancement for LTE applications

被引：9

作者：

Tuffery, A. ^{[1
]}

Deltimple, N. ^{[1
]}

Kerherve, E. ^{[1
]}

Knopik, V. ^{[2
]}

Cathelin, P. ^{[2
]}

机构：

[1] Univ Bordeaux, IMS Lab, Bordeaux INP, CNRS,UMR 5218, Talence, France

[2] STMicroelectronics, Crolles, France

来源：

ELECTRONICS LETTERS | 2015年 / 51卷 / 02期

关键词：

CMOS integrated circuits; power amplifiers; Long Term Evolution; impedance convertors; CMOS fully integrated reconfigurable power amplifier; efficiency enhancement; LTE application; power cell switching technique; high power back-off; distributed active transformer; splitter; combiner; DC bias feed; parallelised power cell; size; 65; nm; frequency; 2; 5; GHz;

D O I：

10.1049/el.2014.3525

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fully integrated power amplifier using a power cell switching technique, implemented in 65 nm CMOS technology is presented. The main objective of the proposed architecture is to significantly improve the efficiency at high power back-off. To do so, distributed active transformers are used as the splitter, the combiner and the DC bias feed to partition the power requirements among the parallelised power cells. An individual cell can be dynamically turned ON/OFF according to the desired output power. At 2.5 GHz, the measured maximum output power is 28.2 dBm and the power-added efficiency is improved for low level, +3.2 and +4.9% for 18 and 23.7 dBm, respectively.

引用

页码：181 / 182

页数：2

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