Voltage-clock scaling for low energy consumption in fixed-priority real-time systems

被引:22
|
作者
Lee, YH
Krishna, CM
机构
[1] Arizona State Univ, Dept Comp Sci & Engn, Tempe, AZ 85287 USA
[2] Univ Massachusetts, Dept Elect & Comp Engn, Amherst, MA 01003 USA
基金
美国国家科学基金会;
关键词
voltage-scaling; scheduling; low-power designs; real-time embedded systems;
D O I
10.1023/A:1022864617640
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Power and energy constraints are becoming increasingly prevalent in real-time embedded systems. Voltage-scaling is a promising technique to reduce energy and power consumption: clock speed tends to decrease linearly with supply voltage while power consumption goes down quadratically. We therefore have a tradeoff between the energy consumption of a task and the speed with which it can be completed. The timing constraints association with real-time tasks can be used to resolve this tradeoff. In this paper, we present two algorithms for voltage-scaling. Assuming that a processor can operate in one of two modes: high voltage and low voltage, we share how to schedule the voltage settings so that deadlines are met while reducing the total energy consumed. We show that significant reductions can be made in energy consumption.
引用
收藏
页码:303 / 317
页数:15
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