Memory Efficient Architecture for Lifting-Based Discrete Wavelet Packet Transform

This brief presents a novel VLSI architecture for computing discrete wavelet packet transform (DWPT) for the continuous flow of data. Each stage of the proposed multi-stage architecture consists of the bit-reordering circuit and serial wavelet filter. The conventional wavelet filter has been modified for single path serial data. The intermediate coefficients are reordered with the help of a bit reordering circuit in order to maintain a continuous flow of data from input to output end with minimum memory and minimum latency. In comparison to the recently published architectures, the proposed one not only reduces the memory requirement by more than 50% but also achieves a 100% hardware utilization ratio. Furthermore, the area and power requirements are reduced by more than 60% and 50%, respectively.